PACK Manufacturing Process Series: Core Functions, System Architecture, and Hardware Structure of Battery Pack BMS

Both power battery packs and energy storage battery packs typically contain dozens or even hundreds of internal cells. To manage such a large number of cells, the Battery Management System (BMS) has become an indispensable key technology.

It can be said that the BMS is the “brain” of the battery pack. Its functions are to ensure personnel and battery safety, meet power or energy storage requirements, and extend battery life.

01 Core Functions of BMS

The core function of BMS is to monitor battery voltage, temperature, and current in real-time, optimize battery performance through State of Charge (SOC) estimation and balancing control, while also possessing fault protection functions such as overvoltage, overcurrent, and overtemperature protection.

Estimating the state of the cells is the core function of the BMS. Achieving this function requires an Analog Front-End (AFE) chip (for voltage acquisition), Hall sensors (for current acquisition), NTC sensors (for temperature acquisition), and other sensors (for acquiring gas pressure, smoke, etc.).

After acquiring the signals, they are combined with electrochemical models and advanced estimation algorithms (such as Extended Kalman Filter, Sliding Mode Observer, etc.) to estimate the battery’s State of Charge (SOC), State of Health (SOH), State of Power (SOP), State of Energy (SOE), and State of Safety (SOS) in real-time.

Based on these state parameters,

a) For the battery pack itself:

The BMS controls and manages the optimization of the battery’s charge and discharge power, limits charge/discharge duration, and interacts via control commands, communication, and diagnostic functions to achieve effective management of the battery’s internal state.

b) For external systems:

Through communication and diagnostic functions, the BMS disseminates key status information and control commands to the vehicle and charger, ensuring coordinated operation between the battery and external systems.

02 System Architecture of BMS

(1) Centralized and Distributed Architectures

Centralized BMS integrates the three functional modules – the Cell Monitoring Unit (CMC), High Voltage Monitoring Unit (HVMU), and Battery Management Unit (BMU) – onto a single circuit board or an integrated controller, forming a “single-point control” architecture.

Centralized BMS results in a compact system structure, reduced cabling, smaller footprint, and relatively lower overall cost. However, since the high-voltage and low-voltage modules are on the same circuit board, special attention must be paid to electrical isolation and safety clearances.

Distributed BMS delegates the acquisition function down to individual battery modules. Multiple Slave Control Units (CMCs) achieve distributed sampling and preliminary data processing, while the Master Control Unit (BMU/BCU) is responsible for system-level management and scheduling, forming a “multi-point acquisition, centralized processing” architecture. This can meet the requirements of large-capacity battery systems, such as numerous acquisition channels and dispersed module placement.

As can be seen from the figure above, the so-called distributed architecture essentially adds a layer of management sub-systems in the middle. These small systems are primarily responsible for collecting information from a portion of the cells, then reporting it via a bus to the BMS control board. The BMS control board then implements comprehensive protection measures, state-of-charge calculations, and other management functions based on the reported information.

Simply put, it’s similar to the organizational structure of a company. When the number of people increases, flat management becomes unreliable in large-scale battery management systems. Therefore, to share the load of the core management board, some sub-tasks are assigned to CSC modules (Cell Supervision Circuits) for privileged management.

Distributed BMS can be further subdivided into: Star-type Distributed, Bus-type Distributed, and Daisy-chain Distributed.

Star-type Distributed: The BMU is located centrally, with each CMC connected directly to the BMU via an independent communication link. This structure offers independent communication links with strong anti-interference capability. However, it requires a bus concentration module, making wiring and interface management relatively complex.

Bus-type Distributed: Multiple CMCs communicate with the BMU via a CAN bus (currently the most widely used BMS communication method). Since all CMCs share the bus, power consumption among nodes is relatively balanced. However, the system heavily relies on the health of the bus; if the bus fails, overall communication may be interrupted.

Daisy-chain Distributed: Multiple CMCs are connected in series in a chain, with data transmitted hop-by-hop along the link to the BMU. This structure offers a simple communication link, saving wiring resources. It is suitable for systems with many modules and a clearly layered battery structure.

(2) Functional Layering

To ensure modularity, scalability, and high reliability, BMS can generally be divided into three layers, as shown in the figure below.

a) Physical Layer: Responsible for acquiring directly measurable external states during battery operation, such as voltage, current, surface temperature, etc., providing data support for upper layers.

b) Core Layer: Responsible for estimating internally unmeasurable states of the battery through models and algorithms, such as SOC and internal cell temperature. This is the critical part of the system.

c) Management Layer: Utilizes the internal state information provided by the core layer to achieve reasonable management of battery charging/discharging and prediction of future operating conditions, ensuring safe and efficient battery operation.

03 Hardware Structure of BMS

The BMS hardware architecture is the physical carrier of its system functions. Hardware design directly affects system accuracy, reliability, and cost. A typical BMS hardware design adopts a distributed architecture, mainly including the Master Control Unit (BMU), Slave Control Units (CSCs), sensor networks, and actuation/protection circuits.

(1) Master Control Unit

Main Control MCU: A high-performance processor supporting ASIL-D functional safety level.
Memory: Flash memory stores parameter configurations and fault logs; RAM is used for real-time data buffering.
Isolated Power Supply: Supplies power to the BMU through a DC/DC isolation module (input voltage is often 12V/24V, output is 3.3V/5V).
Communication Interfaces: CAN transceivers, Ethernet PHY chips.

(2) Slave Control Units

AFE Chips: Dedicated Analog Front-End chips for monitoring series-connected cells.
Voltage Sampling Circuit: Multiplexer switch + precision ADC, using differential sampling to reduce noise.
Temperature Acquisition Circuit: NTC thermistor + voltage divider network, or digital temperature sensors.
Balancing Circuit: Passive balancing: MOSFET + power resistor; Active balancing: Bidirectional DC/DC or capacitor arrays.

(3) Sensors

Hall Sensors: Non-contact measurement, accuracy ±0.5% (used for total current detection).
Shunt Resistors: Low-cost current detection solution, achieving ±0.5% accuracy when paired with a differential amplifier.
Temperature Sensors: NTC/PTC sensors placed at key locations such as cell surfaces, busbars, and heat sinks.

(4) Actuation and Protection Circuits

Relays and Pre-charge Circuit:
Main Relays: High-voltage DC relays controlling the battery pack’s charge/discharge circuit.
Pre-charge Circuit: Uses a pre-charge resistor + contactor for soft-start, preventing inrush current during power-on.
Fuses and Circuit Breakers:
Main Fuse: Fast-acting type for short-circuit fault protection.
Secondary Protection: Resettable fuses (PPTC) to prevent localized overcurrent.